However, in electronic commerce, there is the possibility that an accident or other problem could occur such that the purchased merchandise The present invention relates to a ferroelectric random access memory (FeRAM) device and, more particularly, to a method for manufacturing FeRAM devices utilizing a simplified method of manufacturing the ferroelectric capacitors incorporated therein.
With the improvement in film deposition techniques, research into applications of nonvolatile memory cells using ferroelectric thin films has been increasing. These nonvolatile memory cells utilize the high-speed polarization/inversion and the residual polarization of the ferroelectric capacitor thin films to produce a high-speed rewritable nonvolatile memory cell.
Therefore, ferroelectric random access memories (FeRAM) that incorporate a capacitor thin films having ferroelectric properties, such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT), are becoming more common. The use of a ferroelectric material as the capacitor thin film in place of a conventional silicon oxide film or a silicon nitride film provides improved low-voltage and high-speed performance. Further, the residual polarization of the ferroelectric materials mean that FeRAM do not require a periodic refresh to prevent loss of information during standby intervals like a dynamic random access memory (DRAM). FeRAMs also provide this non-volatile performance without requiring the more complex structure of a conventional SRAM, thereby allowing increased densities.
Since ferroelectric materials have dielectric constants ranging from hundreds to thousands value and stabilized residual polarization properties at room temperature, they are being widely applied in non-volatile memory devices as the capacitor thin film. When a ferroelectric capacitor thin film is used in a non-volatile memory device, information data are stored in dipoles that have been polarized by applying an electric field. Even when electric field is removed, the dipoles retain their residual polarization so the stored information datum, i.e., a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, can be retrieved.
Referring to FIGS. 1A to 1F, there are provided a series of cross-sectional views illustrating a conventional method for manufacturing an FeRAM device incorporating a ferroelectric capacitor.
The manufacturing steps begin with a preparation of an active matrix 110 upon which a number of predetermined manufacturing steps have been carried out. A first insulating layer 112 is then formed on the active matrix 110 and the surface is planarized using a chemical mechanical polishing (CMP) process. Thereafter, a buffer layer, a first conductive layer, a dielectric layer and a second conductive layer are sequentially formed on the first insulating layer.
The second conductive layer is patterned and etched to produce a first predetermined configuration, thereby forming a top electrode 120. Then, the dielectric layer, the first conductive layer and the buffer layer are patterned and etched to produce a second predetermined configuration, thereby forming a ferroelectric capacitor structure comprising a top electrode 120, a capacitor thin film 118, a bottom electrode 116 and a buffer 114, as shown in FIG. 1A.
In a next step, a photoresist layer is formed on the top electrode 120, the capacitor thin film 118 and the first insulating layer 112. This photoresist layer is then patterned to produce a photoresist pattern 122 having a first opening 130, as shown in FIG. 1B.
In an ensuing step, the capacitor thin film 118 is etched to produce a third predetermined configuration using the photoresist pattern 122 as a mask, whereby a portion of the bottom electrode 116 is exposed, as shown in FIG. 1C. Thereafter, the photoresist pattern 122 is removed and the wafer is cleaned using a rinse step to remove etch residues and other particulates.
In a subsequent step, a second insulating layer 124 is formed on the ferroelectric capacitor structure and the first insulating layer 112. A mask layer is then formed on the second insulating layer 124 and patterned to produce a fourth predetermined configuration and to obtain a mask pattern 125, a second opening 135 and the third opening 140, as shown in FIG. 1D.
Thereafter, the second insulating layer is etched using mask pattern 125, after which mask pattern 125 is removed, thereby forming a storage node contact hole 135A and a cell plate contact hole 140A, as shown in FIG. 1E.
Finally, a metal interconnection 126 pattern is formed over the storage node contact hole 135A and the cell plate node contact hole 140A, as shown in FIG. 1F.
According to the conventional method for manufacturing the ferroelectric capacitor, forming the metal interconnection pattern requires that a masking process and an etching process be repeated twice, resulting in a manufacturing process that is undesirably complicated. Further, in addition to the complexity, with the conventional method the cell plate contact hole is twice exposed to the plasma etch for extended periods, greatly increasing the risk of degrading the electrical properties of the bottom electrode.
It is, therefore, an object of the present invention to provide a ferroelectric random access memory (FeRAM) device in which the ferroelectric capacitor structure is produced using a simplified process that preserves the electrical properties of the cell plate contact.
It is another object of the present invention to provide a method for manufacturing the FeRAM device utilizing a simplified process for forming the ferroelectric capacitor structure.
In accordance with these objects, the present invention provides a method for manufacturing a ferroelectric random access memory (FeRAM) device, the method comprising the steps of: a) preparing an active matrix incorporating therein a substrate, a transistor, an isolation region and a first insulating layer; b) forming a ferroelectric capacitor structure, the capacitor structure comprising a buffer formed on the first insulating layer, a bottom electrode formed on the buffer, a capacitor thin film formed on the bottom electrode and a top electrode formed on the capacitor thin film; c) forming a second insulating layer on the top electrode, the capacitor thin film and the first insulating layer; d) forming a photoresist pattern having a first opening and a second opening; e) etching the second insulating layer into the predetermined configuration to open a storage node contact hole and a cell plate contact hole; and f) forming a metal interconnection over the second insulating layer and into the storage node contact hole and the cell plate contact hole.